July 20, 2026
Thermal Design Power: What the Datasheet Doesn’t Tell You
TDP is a design target for the cooling system, not a hard ceiling on what the chip can draw. Sustained real-world workloads regularly exceed it, briefly and by…
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Notes from engineering.
Yield curves, lithography, packaging, and the occasional postmortem — written by the people who did the work.
July 20, 2026
Packaging Is the New Moore’s Law
Transistor density gains are slowing and getting more expensive per generation. Increasingly, the performance win is coming from how the dies are put together, not from the dies…
Read →July 20, 2026
The Real Cost of a Chip Respin
A respin is not "fix the bug and resubmit." It is a new mask set, a new wafer lot, and — if the bug is bad enough —…
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EUV Lithography, Explained Without the Hype
EUV gets described like magic. It is closer to a very expensive, very finicky pinhole camera that happens to use 13.5nm light because nothing else focuses tightly enough.
Read →July 20, 2026
Why Yield Drops Exponentially Past 5nm
Defect density stays roughly flat across a node shrink. Die area does not have to grow for yield to fall off a cliff — it falls because you…
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