Inside the fab

From a raw ingot to a tested package.

Every chip we ship passes through the same seven stages, whether it is a 28nm PMIC or a 3nm flagship SoC. Scroll to walk the line.

01

Ingot

It starts as electronic-grade polysilicon, melted in a quartz crucible, with a tiny seed crystal dipped in and slowly withdrawn while spinning. What comes out is a single, continuous crystal — no grain boundaries — up to two metres long and 300mm across.

02

Wafer

A wire saw slices the ingot into wafers under a millimetre thick, hundreds from a single ingot. Each is lapped, etched, and polished to a flatness measured in nanometres — any topography at this stage becomes a focus error in every layer built on top of it.

03

Lithography

Photoresist is spun onto the wafer, then exposed through a mask that carries one layer of the design. Our finest layers use EUV light at 13.5nm; coarser layers use deep-UV. Exposed resist is developed away, leaving the pattern behind for the next step.

04

Etch

Reactive-ion plasma removes material exactly where the resist has been cleared, carving the pattern into the silicon or the deposited film beneath it. This repeats, layer by layer, sometimes fifty or more times for the most advanced parts.

05

Dope

Ion implantation fires dopant atoms — boron, phosphorus, arsenic — into precise regions at controlled energy and dose, defining where each transistor's junctions sit. A rapid thermal anneal then repairs the crystal lattice and activates the dopants.

06

Package

The finished wafer is diced into individual dies. Good dies are attached to a substrate, connected by wire bonds or solder bumps, and sealed under a lid sized for the part's thermal load — anything from a simple QFN to a multi-die interposer stack.

07

Test

Every single unit is electrically tested before it leaves the building — functional test, speed binning, burn-in for parts that need it. Nothing we have not personally tested reaches a customer's board.

Capabilities

Three fabs, six nodes, one quality bar.

We would rather run fewer nodes well than chase every headline geometry. Every node we operate has been in volume production long enough to have a real reliability track record behind it — except the one we are deliberately still climbing.

6 process nodes in production
3 fabs, worldwide
98.4% line yield, trailing quarter
412 tapeouts shipped to date

What we run today

Six nodes, six different jobs.

28nm Established The workhorse node. Highest yield, lowest cost, decades of characterised IP — this is where power ICs and mixed-signal designs still live. 12nm Balanced General-purpose compute and automotive-grade logic. Enough density for real performance without the frontier-node tapeout bill. 7nm Efficient Our efficiency sweet spot — mobile and edge AI silicon that has to do real inference work inside a coin-cell power budget. 5nm Dense Server-class density. This is the node we reach for when a customer needs raw core count and can pay for the mask set. 3nm Frontier Our flagship SoC node — GAA transistors, the tightest metal pitch we ship today, and a yield curve we are still climbing. 2nm Horizon In risk production now. Early silicon is back from the fab and characterising well — first customer tapeouts open next year.

Want to see a node up close?

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