Why Yield Drops Exponentially Past 5nm

Every process shrink gets pitched as a density win, and it is — but the yield story that comes with it is rarely explained outside a fab.

Yield, in the simplest useful model, follows a Poisson relationship between defect density and die area: the probability a given die is defect-free falls exponentially as either number rises. A shrink doesn’t usually blow up defect density by much on a mature node — but it packs the same defect density into finer features, and finer features are pickier about what counts as a killer defect. A particle that a 12nm line would shrug off can bridge two metal lines at 5nm.

That is the real cost curve customers are paying for on a frontier node: not just the mask set (though that is real too — EUV masks run into eight figures for a full layer set), but a yield ramp that can take two to four quarters to climb from ‘sampling’ to ‘comfortable enough to promise a customer volume.’ Anyone quoting you day-one production pricing on a brand-new node is quoting you a number they plan to lose money on for a year.

We run six nodes for exactly this reason. A 28nm PMIC design doesn’t need to fight that ramp at all — the yield curve there has been flat and high for a decade. Frontier silicon and mature silicon are different businesses wearing the same word, ‘chip.’