Packaging Is the New Moore’s Law

For most of the industry’s history, the way to make a chip faster was to shrink the transistors. That is getting harder and more expensive every generation — which is exactly why so much of our own engineering effort over the last few years has moved from the die to the package around it.

Basalt is the clearest example on our current lineup: rather than a single enormous 5nm die, it’s two identical dies on a passive silicon interposer. Splitting the design this way did two things a monolithic die couldn’t — it kept each individual die small enough to yield well even at a demanding node, and it let us bin the two halves independently before committing them to a package. A defect on one die doesn’t scrap its neighbour.

Obsidian pushes the same idea further: high-bandwidth memory stacked directly on the interposer next to the compute die, rather than routed out to a separate package on the board. The electrical path from compute to memory is now measured in millimetres of interposer trace instead of centimetres of PCB trace, which matters enormously for a workload that spends as much time waiting on memory as it does computing.

None of this shows up as a smaller transistor. It shows up as a smarter arrangement of the transistors you already have — and it’s a big part of why our packaging engineering headcount has roughly doubled in three years while our transistor-design headcount has grown much more slowly.